The semiconductor industry has experienced rapid growth due to improvements in the integration density of a variety of electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). For the most part, this improvement in integration density has come from shrinking the semiconductor process node (e.g., shrinking the process node towards the sub-20 nm node). As device dimensions shrink, voltage nodes also shrink, with modern core device voltages trending toward less than 1 Volt, and input/output (I/O) device voltages under 2 Volts. Devices operating at such low voltages are sensitive to high voltages, which worsens reliability concerns for legacy systems that move to new process nodes while maintaining old system voltage parameters (e.g., using 1.8V devices in 5V system applications).
One danger to integrated circuits in nearly all process nodes is electrostatic discharge, or ESD. When an ESD event occurs, a large amount of charge builds up rapidly at a circuit node, such as a pad, which has the potential of introducing a very high voltage that will damage integrated circuit devices if not mitigated. ESD protection circuits are often designed into integrated circuits to rapidly sense and respond to the ESD charge by draining the charge to ground before devices in the integrated circuit are damaged. Because ESD circuits are expected to handle large voltage spikes, they are typically very large. And, with greater device sensitivity to high voltages, ESD circuits are even more likely to encounter reliability issues.